Device and circuit performance analysis of double gate junctionless transistors at L g = 18 nm
نویسندگان
چکیده
منابع مشابه
Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10(15)) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off...
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ژورنال
عنوان ژورنال: The Journal of Engineering
سال: 2014
ISSN: 2051-3305,2051-3305
DOI: 10.1049/joe.2013.0269